The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a method for post lithographic critical dimension shrinking including a thermal reflow process.
The fabrication of integrated circuits on a semiconductor substrate typically includes multiple photolithography steps. A photolithography process begins by applying a thin layer of a photoresist material to the substrate surface. The photoresist is then exposed through a photolithography exposure tool to a radiation source that changes the solubility of the photoresist at areas exposed to the radiation. The photolithography exposure tool typically includes transparent regions that do not interact with the exposing radiation and a patterned material or materials that do interact with the exposing radiation, either to block it or to shift its phase.
As each successive generation of integrated circuits crowds more circuit elements onto the semiconductor substrate, it becomes necessary to reduce the size of the features, i.e., the lines and spaces that make up the circuit elements. The minimum feature size that can be accurately produced on a substrate is limited by the ability of the fabrication process to form an undistorted optical image of the mask pattern onto the substrate, by the chemical and physical interaction of the photoresist with the developer, and by the uniformity of the subsequent process (e.g., etching or diffusion) that uses the patterned photoresist.
Advanced lithography processes are extremely expensive and have driven exponential cost increases in semiconductor manufacturing. As such, advanced lithography for formation of structures such as contact holes has become increasingly reliant on “shrink” methods in which a contact hole is imaged at a critical dimension (CD) larger than the target dimension, and is thereafter reduced to the target dimension through some post-lithography process. Many different processes are under development/exploration by resist vendors, as well as device manufacturers, using a wide range of techniques including reflow, etch tapering in intermediate layers, and overcoats that bind to the existing pattern with finite thickness.
In particular, thermal reflow processes can enable dramatic cost savings by allowing lithographic images at dimensions well above the target CD and subsequently achieving the target CD by “reflow” of the resist material to drive a lateral shrink. This can defer the need for costly mask technologies, or advanced lithography tooling, leading to lower process cost of ownership. It is a particularly promising technique for contact and via level formation.
Unfortunately, conventional thermal reflow commonly suffers profile degradation during the thermal flow step. More specifically, severe “footing” is observed wherein gravitational flow accumulates resist at the lower part of the feature while also laterally shrinking the feature. This effect is one of the most significant limitations to implementation of thermal flow processes, since the resulting degraded profile impairs the reactive ion etch (RIE) process, leading to line edge roughness and highly tapered profiles following the etch.